1. Field of the Invention
This invention relates to semiconductor memory units and, more particularly, to circuits which detect transitions associated with address signals and generate output pulse signals controlling the activity associated with the addressing function. Based on the detected signals, these circuits generate resulting signals which determine the subsequent operation in the semiconductor memory unit.
2. Description of the Related Art
Referring to FIG. 1, an address transition detection summing circuit, according to the prior art, is shown. A control signal is applied through delay unit 11 and delay unit 12 to a first input terminal of logic NOR gate 13. Address signals are applied to the input terminal of summing network 10. In the summing network 10, the address signals are applied to the gate terminals of a series of transistors 102 through 104. The transistors 102 through 104 have one terminal coupled to ground and a second terminal coupled to both a load resistor 101 and the input terminal of inverting amplifier 105. The output terminal of inverting amplifier 105 is coupled to the output terminal of summing network 10. The output terminal of summing network 10 is coupled to a second input terminal of logic NOR gate 13. The output terminal of logic NOR gate 13 is applied through inverting amplifier 14 and inverting amplifier 15 to an output address signal terminal of the address transition detection summing circuit.
Referring to FIG. 2, the disadvantages associated with the use of the address transition detection summing circuit of FIG. 1 are illustrated. The curve labelled A in FIG. 2 is the leading edge of the address signal detected and processed by the address transition detection summing circuit. The detection circuitry generates a output signal pulse that has a leading edge developed when the leading edge of the address signal passes through the detection level (cf. FIG. 2) and the trailing edge of the output signal pulse is developed when the address signal passes through the detection level for a second time. In the typical address signal, the final portion of the address transition pulse is given by curve A(1). As will be clear from FIG. 2, the address transition detection summing circuit will result in a pulse having a total width of t2. The width of the pulse is determined by the width of the address signal plus a contribution having duration t3 resulting from the parameters of the summing network 10. However, should a "glitch" occur in an address signal and in the absence of applied simultaneous longer address signals, the trailing edges of the shorted address transition pulses can be represented by A(2) or A(3). As will be clear from FIG. 2, an address signal with a trailing edge A(2) will result in a pulse having a width of t1, while an address signal having a trailing edge A(3) will result in a pulse from the address transition detection circuit with a width of t0.
The summing circuit 10 (in FIG. 1) is generally referred to as a wired-OR summing circuit and is selected because of the relatively low number of transistors used in the implementation and the speed with which an output pulse is generated. When a "glitch" occurs, the output signals generated by the address transition detection summing circuit can be appreciably narrowed over the expected pulse. The output signals from the address detection transition circuit are used to precharge internal input/output lines. These input/output lines are typically heavily capacitively loaded when switching from one memory location to another. The output signal pulse width often controls the duration of the precharge during the memory location switching. This pulse width often controls the activation of intermediate input/output buffers as well, turning the buffers off while the equalization is accomplished and then reactivating the buffers once the new data has been placed on the input/output lines. The major disadvantage of this type of summing circuit is the susceptibility to output signal pulse width variations. The load resistor 101 in the summing circuit of FIG. 1 is included to reduce the variation in pulse width that occurs with metal-oxide-semiconductor transistor loads as a function of fabrication process variations, temperature variations, and operating conditions. However, the use of a load resistor does not eliminate the variation in the output signal that occurs as a result of the address signal pulse width variation. The width of the output signal pulses from the address transition detection summing circuit are a function of the amplitude and duration of the address signal "glitches". The narrow output pulse widths from the address transition detection summing circuit can cause a circuit malfunction due to inadequate input/output precharge and insufficient time to establish a proper signal level on the input/output lines before activation of the input/output amplifiers.
A need has therefore been felt for apparatus and a related method to insure that the output signal from the address transition detection summing circuit has a sufficient output signal pulse width to prevent a resulting circuit malfunction.